82NM10 Datasheet, PDF (350/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI-to-PCI Bridge Registers (D30:F0)
Bit
Description
2 ISA Enable (IE) — R/W. This bit only applies to I/O addresses that are enabled by
the I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space. If this
bit is set, the Chipset PCI bridge will block any forwarding from primary to secondary of
I/O transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to
3FFh).
1 SERR# Enable (SEE) — R/W. This bit controls the forwarding of secondary interface
SERR# assertions on the primary interface. When set, the PCI bridge will forward
SERR# pin.
• SERR# is asserted on the secondary interface.
• This bit is set.
• CMD.SEE (D30:F0:04 bit 8) is set.
0 Parity Error Response Enable (PERE) — R/W.
0 = Disable
1 = The Chipset PCI bridge is enabled for parity error reporting based on parity errors
on the PCI bus.
12.1.20 SPDH—Secondary PCI Device Hiding Register
(PCI-PCI—D30:F0)
Offset Address: 40h–41h
Default Value: 00h
Attribute:
Size:
R/W, RO
16 bits
This register allows software to hide the PCI devices, either plugged into slots or on the
motherboard.
Bit
Description
15:8
7
6
5
4
3
2
1
0
Reserved
Hide Device 7 (HD7) — R/W, RO. Same as bit 0 of this register, except for device 7
(AD[23])
Hide Device 6 (HD6) — R/W, RO. Same as bit 0 of this register, except for device 6
(AD[22])
Hide Device 5 (HD5) — R/W, RO. Same as bit 0 of this register, except for device 5
(AD[21])
Hide Device 4 (HD4) — R/W, RO. Same as bit 0 of this register, except for device 4
(AD[20])
Hide Device 3 (HD3) — R/W, RO. Same as bit 0 of this register, except for device 3
(AD[19])
Hide Device 2 (HD2) — R/W, RO. Same as bit 0 of this register, except for device 2
(AD[18])
Hide Device 1 (HD1) — R/W, RO. Same as bit 0 of this register, except for device 1
(AD[17])
Hide Device 0 (HD0) — R/W, RO.
0 = The PCI configuration cycles for this slot are not affected.
1 = Chipset hides device 0 on the PCI bus. This is done by masking the IDSEL (keeping
it low) for configuration cycles to that device. Since the device will not see its
IDSEL go active, it will not respond to PCI configuration cycles and the processor
will think the device is not present. AD[16] is used as IDSEL for device 0.
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Datasheet