82NM10 Datasheet, PDF (282/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Chipset Configuration Registers
10.1.36 TCTL—TCO Configuration Register
Offset Address: 3000–3000h
Default Value: 00h
Attribute:
Size:
R/W
8-bit
Bit
Description
7
TCO IRQ Enable (IE) — R/W.
0 = TCO IRQ is disabled.
1 = TCO IRQ is enabled, as selected by the TCO_IRQ_SEL field.
6:3 Reserved
2:0 TCO IRQ Select (IS) — R/W. Specifies on which IRQ the TCO will internally appear.
If not using the APIC, the TCO interrupt must be routed to IRQ9-11, and that
interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI
interrupts. If using the APIC, the TCO interrupt can also be mapped to IRQ20-23, and
can be shared with other interrupt.
000 = IRQ 9
001 = IRQ 10
010 = IRQ 11
011 = Reserved
100 = IRQ 20 (only if APIC enabled)
101 = IRQ 21 (only if APIC enabled)
110 = IRQ 22 (only if APIC enabled)
111 = IRQ 23 (only if APIC enabled)
NOTE: When setting the these bits, the IE bit should be cleared to prevent glitching.
NOTE: When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should
be programmed for active-high reception. When the interrupt is mapped to
APIC interrupts 20 through 23, the APIC should be programmed for active-
low reception.
10.1.37 D31IP—Device 31 Interrupt Pin Register
Offset Address: 3100–3103h
Default Value: 00042210h
Attribute:
Size:
R/W, RO
32-bit
Bit
Description
31:16
15:12
Reserved
SM Bus Pin (SMIP) — R/W. This field indicates which pin the SMBus controller
drives as its interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
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Datasheet