82NM10 Datasheet, PDF (424/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Bit
31:16
Description
GPIOn_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = These bits are set any time the corresponding GPIO is set up as an input and the
corresponding GPIO signal is high (or low if the corresponding GP_INV bit is
set). If the corresponding enable bit is set in the GPE0_EN register, then when
the GPIO[n]_STS bit is set:
• If the system is in an S1–S5 state, the event will also wake the system.
• If the system is in an S0 state (or upon waking back to an S0 state), a SCI will
be caused depending on the GPIO_ROUT bits (D31:F0:B8h, bits 31:30) for the
corresponding GPI.
NOTE: Mapping is as follows: bit 31 corresponds to GPIO15... and bit 16
corresponds to GPIO0.
15
Reserved
14
USB4_STS — R/WC.
0 = Disable.
1 = Set by hardware and can be reset by writing a one to this bit position or a
resume well reset. This bit is set when USB UHCI controller #4 needs to cause a
wake. Additionally if the USB4_EN bit is set, the setting of the USB4_STS bit will
generate a wake event.
13
PME_B0_STS — R/WC. This bit will be set to 1 by the Chipset when any internal
device with PCI Power Management capabilities on bus 0 asserts the equivalent of
the PME# signal. Additionally, if the PME_B0_EN bit is set, and the system is in an
S0 state, then the setting of the PME_B0_STS bit will generate an SCI (or SMI# if
SCI_EN is not set). If the PME_B0_STS bit is set, and the system is in an S1–S4
state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the
PME_B0_STS bit will generate a wake event, and an SCI (or SMI# if SCI_EN is not
set) will be generated. If the system is in an S5 state due to power button override,
then the PME_B0_STS bit will not cause a wake event or SCI.
12
11
10
(Nettop
Only)
The default for this bit is 0. Writing a 1 to this bit position clears this bit.
USB3_STS — R/WC.
0 = Disable.
1 = Set by hardware and can be reset by writing a one to this bit position or a
resume well reset. This bit is set when USB UHCI controller #3 needs to cause a
wake. Additionally if the USB3_EN bit is set, the setting of the USB3_STS bit will
generate a wake event.
PME_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN
bit is set, and the system is in an S0 state, then the setting of the PME_STS bit
will generate an SCI or SMI# (if SCI_EN is not set). If the PME_EN bit is set, and
the system is in an S1–S4 state (or S5 state due to setting SLP_TYP and
SLP_EN), then the setting of the PME_STS bit will generate a wake event, and
an SCI will be generated. If the system is in an S5 state due to power button
override or a power failure, then PME_STS will not cause a wake event or SCI.
Reserved
424
Datasheet