82NM10 Datasheet, PDF (372/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.1.29 BIOS_CNTL—BIOS Control Register
(LPC I/F—D31:F0)
Offset Address: DCh
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/WLO, R/W, RO
8 bit
Core
Bit
Description
7:5
Reserved
4
Top Swap Status (TSS)— RO: This bit provides a read-only path to view the state
of the Top Swap bit that is at offset 3414h, bit 0.
3:2
SPI Read Configuration (SRC)— R/W: This 2-bit field controls two policies related
to BIOS reads on the SPI interface:
Bit 3- Prefetch Enable
Bit 2- Cache Disable
Settings are summarized below:
Bits 3:2
00b
01b
10b
11b
Description
No prefetching, but caching enabled. 64B demand reads
load the read buffer cache with “valid” data, allowing repeated
code fetches to the same line to complete quickly
No prefetching and no caching. One-to-one
correspondence of host BIOS reads to SPI cycles. This value
can be used to invalidate the cache.
Prefetching and Caching enabled. This mode is used for
long sequences of short reads to consecutive addresses (i.e.,
shadowing).
Reserved. This is an invalid configuration, caching must
be enabled when prefetching is enabled.
1
BIOS Lock Enable (BLE) — R/WLO.
0 = Setting the BIOSWE will not cause SMIs.
1 = Enables setting the BIOSWE bit to cause SMIs. Once set, this bit can only be
cleared by a PLTRST#
0
BIOS Write Enable (BIOSWE) — R/W.
0 = Only read cycles permitted to Firmware Hub or SPI flash.
1 = Access to the BIOS space is enabled for both read and write cycles. When this
bit is written from a 0 to a 1 and BIOS Lock Enable (BLE) is also set, an SMI#
is generated. This ensures that only SMI code can update BIOS.
NOTE: Writes to the Firmware Hub’s Feature Space are not blocked when the
BIOSWE is cleared in order to allow access to registers. The Feature Space
is the second range that is located 4 MB below the BIOS range for each
Firmware Hub.
372
Datasheet