82NM10 Datasheet, PDF (491/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15.1.36 SIRI—SATA Indexed Registers Index
Address Offset: A0h
Default Value: 00h
.
Bit
Attribute:
Size:
Description
R/W
8 bits
7:2 Index (IDX) — R/W. This field contains a 6-bit index pointer into the SATA Indexed
Register space. Data is written into and read from the SIRD register (D31:F2:A4h).
1:0 Reserved
SATA Indexed Registers
Index
Name
00h–03h SATA TX Termination Test Register 1 (STTT1)
04h–1Bh Reserved
1Ch–1Fh SATA Test Mode Enable Register (STME)
20h–73h Reserved
74h–77h SATA TX Termination Test Register 2 (STTT2)
78h–FFh Reserved
15.1.37 STRD—SATA Indexed Register Data
Address Offset: A4h
Default Value: XXXXXXXXh
Attribute:
Size:
R/W
32 bits
Bit
Description
31:0 Data (DTA) — R/W. This field contains a 32-bit data value that is written to the register
pointed to by SIRI (D31:F2;A0h) or read from the register pointed to by SIRI.
15.1.37.1 STTT1—SATA Indexed Registers Index 00h
(SATA TX Termination Test Register 1)
Address Offset: Index 00h–03h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
.
Bit
Description
31:2
1
Reserved.
Port 1 TX Termination Test Enable — R/W:
0 = Port 1 TX termination port testing is disabled.
1 = Enables testing of Port 1 TX termination.
NOTE: This bit only to be used for system board testing.
0 Port 0 TX Termination Test Enable — R/W:
0 = Port 0 TX termination port testing is disabled.
1 = Enables testing of Port 0 TX termination.
NOTE: This bit only to be used for system board testing.
Datasheet
491