82NM10 Datasheet, PDF (260/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Register and Memory Mapping
Table 9-107.Fixed I/O Ranges Decoded by Chipset (Sheet 3 of 3)
I/O
Address
A0h–A1h
A4h–A5h
A8h–A9h
ACh–ADh
B0h–B1h
B2h–B3h
Read Target
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Power Management
Write Target
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Power Management
B4h–B5h
B8h–B9h
BCh–BDh
C0h–D1h
D2h–DDh
DEh–DFh
F0h
170h–177h
1F0h–1F7h
376h
3F6h
4D0h–4D1h
CF9h
Interrupt Controller
Interrupt Controller
Interrupt Controller
DMA Controller
RESERVED
DMA Controller
FERR#/IGNNE# / Interrupt
Controller
IDE Controller, SATA
Controller, or PCI
IDE Controller, SATA
Controller, or PCI ¹
IDE Controller, SATA
Controller, or PCI
IDE Controller, SATA
Controller, or PCI ¹
Interrupt Controller
Reset Generator
Interrupt Controller
Interrupt Controller
Interrupt Controller
DMA Controller
DMA Controller
DMA Controller
FERR#/IGNNE# /
Interrupt Controller
SATA Controller, or PCI
SATA Controller, or PCI
SATA Controller, or PCI
SATA Controller, or PCI
Interrupt Controller
Reset Generator
Internal Unit
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Power
Management
Interrupt
Interrupt
Interrupt
DMA
DMA
DMA
Processor I/F
Forwarded to IDE
or SATA
Forwarded to IDE
or SATA
Forwarded to IDE
or SATA
Forwarded IDE or
SATA
Interrupt
Processor I/F
NOTES:
1.
A read to this address will subtractively go to PCI, where it will master abort.
9.3.2 Variable I/O Decode Ranges
Table 9-108 shows the Variable I/O Decode Ranges. They are set using Base Address
Registers (BARs) or other configuration bits in the various PCI configuration spaces.
The PNP software (PCI or ACPI) can use their configuration mechanisms to set and
adjust these values.
Warning: The Variable I/O Ranges should not be set to conflict with the Fixed I/O Ranges.
Unpredictable results if the configuration software allows conflicts to occur. The Chipset
does not perform any checks for conflicts.
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Datasheet