82NM10 Datasheet, PDF (258/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Register and Memory Mapping
Some of the PCI registers contain reserved bits. Software must deal correctly with
fields that are reserved. On reads, software must use appropriate masks to extract the
defined bits and not rely on reserved bits being any particular value. On writes,
software must ensure that the values of reserved bit positions are preserved. That is,
the values of reserved bit positions must first be read, merged with the new values for
other bit positions and then written back. Note the software does not need to perform
read, merge, write operation for the configuration address register.
In addition to reserved bits within a register, the configuration space contains reserved
locations. Software should not write to reserved PCI configuration locations in the
device-specific region (above address offset 3Fh).
9.3
I/O Map
The I/O map is divided into Fixed and Variable address ranges. Fixed ranges cannot be
moved, but in some cases can be disabled. Variable ranges can be moved and can also
be disabled.
9.3.1
Fixed I/O Address Ranges
Table 9-107 shows the Fixed I/O decode ranges from the processor perspective. Note
that for each I/O range, there may be separate behavior for reads and writes. DMI
(Direct Media Interface) cycles that go to target ranges that are marked as “Reserved”
will not be decoded by the Chipset, and will be passed to PCI unless the Subtractive
Decode Policy bit is set (D31:F0:Offset 42h, bit 0). If a PCI master targets one of the
fixed I/O target ranges, it will be positively decoded by the Chipset in medium speed.
Address ranges that are not listed or marked “Reserved” are not decoded by the
Chipset (unless assigned to one of the variable ranges).
Table 9-107.Fixed I/O Ranges Decoded by Chipset (Sheet 1 of 3)
I/O
Address
Read Target
Write Target
00h–08h
09h–0Eh
0Fh
10h–18h
19h–1Eh
1Fh
20h–21h
24h–25h
28h–29h
2Ch–2Dh
2E–2F
DMA Controller
RESERVED
DMA Controller
DMA Controller
RESERVED
DMA Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
LPC SIO
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
LPC SIO
Internal Unit
DMA
DMA
DMA
DMA
DMA
DMA
Interrupt
Interrupt
Interrupt
Interrupt
Forwarded to LPC
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Datasheet