82NM10 Datasheet, PDF (295/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Chipset Configuration Registers
10.1.51 BUC—Backed Up Control Register
Offset Address: 3414–3414h
Default Value: 0000001xb
Attribute:R/W
All bits in this register are in the RTC well and only cleared by RTCRST#.
Bit
Description
7:3 Reserved
2
CPU BIST Enable (CBE) — R/W. This bit is in the resume well and is reset by RSMRST#, but not
PLTRST# nor CF9h writes.
0 = Disabled.
1 = The INIT# signals will be driven active when CPURST# is active. INIT# and INIT3_3V# will go
inactive with the same timings as the other processor I/F signals (hold time after CPURST#
inactive).
1
Reserved
0
Top Swap (TS) — R/W.
0 = Chipset will not invert A16.
1 = Chipset will invert A16 for cycles going to the BIOS space (but not the feature space) in the
FWH.
If the Chipset is strapped for Top-Swap (STRAP0# is low at rising edge of PWROK), then this bit
cannot be cleared by software. The strap jumper should be removed and the system rebooted.
10.1.52 FD—Function Disable Register
Offset Address: 3418–341Bh
Default Value: See bit description
Attribute:
Size:
R/W, RO
32-bit
The UHCI functions must be disabled from highest function number to lowest. For
example, if only three UHCIs are wanted, software must disable UHCI #4 (UD4 bit set).
When disabling UHCIs, the EHCI Structural Parameters Registers must be updated with
coherent information in “Number of Companion Controllers” and “N_Ports” fields.
When disabling a function, only the configuration space is disabled. Software must
ensure that all functionality within a controller that is not desired (such as memory
spaces, I/O spaces, and DMA engines) is disabled prior to disabling the function.
When a function is disabled, software must not attempt to re-enable it. A disabled
function can only be re-enabled by a platform reset.
Bit
31:20
19
18
Description
Reserved
PCI Express 4 Disable (PE4D) — R/W. When disabled, the link for this port is put
into the “link down” state.
0 = PCI Express* port #4 is enabled. (Default)
1 = PCI Express port #4 is disabled.
PCI Express 3 Disable (PE3D) — R/W. When disabled, the link for this port is put
into the link down state.
0 = PCI Express port #3 is enabled. (Default)
1 = PCI Express port #3 is disabled.
Datasheet
295