82NM10 Datasheet, PDF (593/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Intel HD Audio Controller Registers (D27:F0)
Table 18-147.Intel HD Audio PCI Register Address Map
(Intel HD Audio D27:F0) (Sheet 2 of 5)
HDBAR +
Offset
Mnemonic
Register Name
44h–47h
48h–49h
4Ah–4Bh
4Ch
4Dh
4Eh
50h–53h
54h–57h
58h–59h
5Ah–5Bh
5Ch
5Dh
5Eh
60h–63h
64h–67h
68h–69h
CORBUBASE
CORBWP
CORBRP
CORBCTL
CORBST
CORBSIZE
RIRBLBASE
RIRBUBASE
RIRBWP
RINTCNT
RIRBCTL
RIRBSTS
RIRBSIZE
IC
IR
IRS
CORB Upper Base Address
CORB Write Pointer
CORB Read Pointer
CORB Control
CORB Status
CORB Size
RIRB Lower Base Address
RIRB Upper Base Address
RIRB Write Pointer
Response Interrupt Count
RIRB Control
RIRB Status
RIRB Size
Immediate Command
Immediate Response
Immediate Command Status
70h–73h
74h–77h
80–82h
83h
84h–87h
88h–8Bh
8Ch–8Dh
8Eh–8F
90h–91h
92h–93h
98h–9Bh
9Ch–9Fh
A0h–A2h
A3h
A4h–A7h
A8h–ABh
DPLBASE
DPUBASE
ISD0CTL
ISD0STS
ISD0LPIB
ISD0CBL
ISD0LVI
ISD0FIFOW
ISD0FIFOS
ISD0FMT
ISD0BDPL
ISD0BDPU
ISD1CTL
ISD1STS
ISD1LPIB
ISD1CBL
DMA Position Lower Base Address
DMA Position Upper Base Address
Input Stream Descriptor 0 (ISD0)
Control
ISD0 Status
ISD0 Link Position in Buffer
ISD0 Cyclic Buffer Length
ISD0 Last Valid Index
ISD0 FIFO Watermark
ISD0 FIFO Size
ISD0 Format
ISD0 Buffer Descriptor List Pointer-
Lower Base Address
ISD0 Buffer Description List Pointer-
Upper Base Address
Input Stream Descriptor 1(ISD01)
Control
ISD1 Status
ISD1 Link Position in Buffer
ISD1 Cyclic Buffer Length
Default
Access
00000000h
0000h
0000h
00h
00h
42h
00000000h
00000000h
0000h
0000h
00h
00h
42h
00000000h
00000000h
0000h
00000000h
00000000h
040000h
R/W
R/W
R/W
R/W
R/WC
RO
R/W, RO
R/W
R/W, RO
R/W
R/W
R/WC
RO
R/W
RO
R/W, R/
WC
R/W, RO
R/W
R/W, RO
00h
00000000h
00000000h
0000h
0004h
0077h
0000h
00000000h
R/WC, RO
RO
R/W
R/W
R/W
RO
R/W
R/W, RO
00000000h
R/W
040000h R/W, RO
00h
00000000h
00000000h
R/WC, RO
RO
R/W
Datasheet
593