82NM10 Datasheet, PDF (101/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.5.1.12
when the core logic is reset (via CF9h, PWROK, or SYS_RESET#, etc.). This is not
inconsistent with the LPC LPCPD# protocol.
Configuration and Chipset Implications
Note:
LPC Interface Decoders
To allow the I/O cycles and memory mapped cycles to go to the LPC interface, Chipset
includes several decoders. During configuration, Chipset must be programmed with the
same decode ranges as the peripheral. The decoders are programmed via the Device
31:Function 0 configuration space.
Chipset cannot accept PCI write cycles from PCI-to-PCI bridges or devices with similar
characteristics (specifically those with a “Retry Read” feature which is enabled) to an
LPC device if there is an outstanding LPC read cycle towards the same PCI device or
bridge. These cycles are not part of normal system operation, but may be encountered
as part of platform validation testing using custom test fixtures.
Bus Master Device Mapping and START Fields
Bus Masters must have a unique START field. In the case of Chipset that supports two
LPC bus masters, it drives 0010 for the START field for grants to bus master #0
(requested via LDRQ0#) and 0011 for grants to bus master #1 (requested via
LDRQ1#.). Thus, no registers are needed to configure the START fields for a particular
bus master.
5.5.2
SERR# Generation
Several internal and external sources of the LPC Bridge can cause SERR#, as described
below.
The first class of errors is parity errors related to the backbone. The LPC Bridge
captures generic data parity errors (errors it finds on the backbone) as well as errors
returned on the backbone cycles where the bridge was the master and parity error
response is enabled. If either of these two conditions is met, and with SERR# enable
(PCICMD.SERR_EN) set, SERR# will be captured.
Additionally, if the LPC Bridge receives an error SYNC on LPC bus, an SERR# will also
be generated.
Datasheet
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