82NM10 Datasheet, PDF (160/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.15
Note:
System Management (D31:F0)
Chipset provides various functions to make a system easier to manage and to lower the
Total Cost of Ownership (TCO) of the system. In addition, Chipset provides integrated
ASF Management support. Features and functions can be augmented via external A/D
converters and GPIO, as well as an external microcontroller.
The following features and functions are supported by Chipset:
• Processor present detection
— Detects if processor fails to fetch the first instruction after reset
• Various Error detection (such as ECC Errors) Indicated by host controller
— Can generate SMI#, SCI, SERR, NMI, or TCO interrupt
• Intruder Detect input
— Can generate TCO interrupt or SMI# when the system cover is removed
— INTRUDER# allowed to go active in any power state, including G3
• Detection of bad Firmware Hub programming
— Detects if data on first read is FFh (indicates unprogrammed Firmware Hub)
• Ability to hide a PCI device
— Allows software to hide a PCI device in terms of configuration space through the
use of a device hide register (See Section 10.1.52)
• Integrated ASF Management support
Voltage ID from the processor can be read via GPI signals.
5.15.1
Theory of Operation
The System Management functions are designed to allow the system to diagnose failing
subsystems. The intent of this logic is that some of the system management
functionality be provided without the aid of an external microcontroller.
5.15.1.1
Detecting a System Lockup
When the processor is reset, it is expected to fetch its first instruction. If the processor
fails to fetch the first instruction after reset, the TCO timer times out twice and Chipset
asserts PLTRST#.
5.15.1.2
Handling an Intruder
Chipset has an input signal, INTRUDER#, that can be attached to a switch that is
activated by the system’s case being open. This input has a two RTC clock debounce. If
INTRUDER# goes active (after the debouncer), this will set the INTRD_DET bit in the
TCO_STS register. The INTRD_SEL bits in the TCO_CNT register can enable Chipset to
cause an SMI# or interrupt. The BIOS or interrupt handler can then cause a transition
to the S5 state by writing to the SLP_EN bit.
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Datasheet