82NM10 Datasheet, PDF (407/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Bit
Description
6:5 CPU PLL Lock Time (CPLT) — R/W. This field indicates the amount of time that the
processor needs to lock its PLLs. This is used wherever timing t270 (Chapter 20)
applies.
00 = min 30.7 µs (Default)
01 = min 61.4 µs
10 = min 122.8 µs
11 = min 245.6 µs
It is the responsibility of the BIOS to program the correct value in this field prior to the
first transition to C3 or C4 states (or performing Intel SpeedStep^® technology
transitions).
NOTE: The new DPSLP-TO-SLP bits (D31:FO:AAh, bits 1:0) act as an override to these
bits.
NOTE: These bits are not cleared by any type of reset except RSMRST# or a CF9 write
4 System Reset Status (SRS) — R/WC. Software clears this bit by writing a 1 to it.
0 = SYS_RESET# button Not pressed.
1 = Chipset sets this bit when the SYS_RESET# button is pressed. BIOS is expected to
read this bit and clear it, if it is set.
NOTE: This bit is also reset by RSMRST# and CF9h resets.
3 CPU Thermal Trip Status (CTS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when PLTRST# is inactive and THRMTRIP# goes active while the
system is in an S0 or S1 state.
NOTES:
1.
This bit is also reset by RSMRST#, and CF9h resets. It is not reset by the
shutdown and reboot associated with the CPUTHRMTRIP# event.
2.
The CF9h reset in the description refers to CF9h type core well reset which
includes SYS_RST#, PWROK/VRMPWRGD low, SMBus hard reset, TCO Timeout.
This type of reset will clear CTS bit.
2 Minimum SLP_S4# Assertion Width Violation Status — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Hardware sets this bit when the SLP_S4# assertion width is less than the time
programmed in the SLP_S4# Minimum Assertion Width field (D31:F0:Offset
A4h:bits 5:4). The Chipset begins the timer when SLP_S4# is asserted during S4/
S5 entry, or when the RSMRST# input is deasserted during G3 exit. Note that this
bit is functional regardless of the value in the SLP_S4# Assertion Stretch Enable
(D31:F0:Offset A4h:bit 3).
NOTE: This bit is reset by the assertion of the RSMRST# pin, but can be set in some
cases before the default value is readable.
1 CPU Power Failure (CPUPWR_FLR) — R/WC.
0 = Software (typically BIOS) clears this bit by writing a 0 to it.
1 = Indicates that the VRMPWRGD signal from the processor’s VRM went low while the
system was in an S0 or S1 state.
NOTE: VRMPWRGD is sampled using the RTC clock. Therefore, low times that are less
than one RTC clock period may not be detected by the Chipset.
Datasheet
407