82NM10 Datasheet, PDF (461/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

UHCI Controllers Registers
Bit
Description
0 Run/Stop (RS) — R/W. When set to 1, the Chipset proceeds with execution of the
schedule. The Chipset continues execution as long as this bit is set. When this bit is
cleared, the Chipset completes the current transaction on the USB and then halts. The
HC Halted bit in the status register indicates when the host controller has finished the
transaction and has entered the stopped state. The host controller clears this bit when
the following fatal errors occur: consistency check failure, PCI Bus errors.
0 = Stop
1 = Run
NOTE: This bit should only be cleared if there are no active Transaction Descriptors in
the executable schedule or software will reset the host controller prior to setting
this bit again.
Table 14-134.Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0)
Operation
SWDBG Run/Stop
(Bit 5)
(Bit 0)
Description
0
0
If executing a command, the host controller completes the command
and then stops. The 1.0 ms frame counter is reset and command list
execution resumes from start of frame using the frame list pointer
selected by the current value in the FRNUM register. (While Run/
Stop=0, the FRNUM register (D29:F0/F1/F2/F3:BASE + 06h) can be
reprogrammed).
0
1
Execution of the command list resumes from Start Of Frame using the
frame list pointer selected by the current value in the FRNUM register.
The host controller remains running until the Run/Stop bit is cleared
(by software or hardware).
1
0
If executing a command, the host controller completes the command
and then stops and the 1.0 ms frame counter is frozen at its current
value. All status are preserved. The host controller begins execution
of the command list from where it left off when the Run/Stop bit is
set.
1
1
Execution of the command list resumes from where the previous
execution stopped. The Run/Stop bit is set to 0 by the host controller
when a TD is being fetched. This causes the host controller to stop
again after the execution of the TD (single step). When the host
controller has completed execution, the HC Halted bit in the Status
Register is set.
When the USB host controller is in Software Debug Mode (USBCMD Register bit 5=1),
the single stepping software debug operation is as follows:
To Enter Software Debug Mode:
1. HCD puts host controller in Stop state by setting the Run/Stop bit to 0.
2. HCD puts host controller in Debug Mode by setting the SWDBG bit to 1.
3. HCD sets up the correct command list and Start Of Frame value for starting point in
the Frame List Single Step Loop.
4. HCD sets Run/Stop bit to 1.
Datasheet
461