82NM10 Datasheet, PDF (256/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Register and Memory Mapping
9
9.1
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Register and Memory Mapping
The Chipset contains registers that are located in the processor’s I/O space and
memory space and sets of PCI configuration registers that are located in PCI
configuration space. This chapter describes the Chipset I/O and memory maps at the
register-set level. Register access is also described. Register-level address maps and
Individual register bit descriptions are provided in the following chapters. The following
notations and definitions are used in the register/instruction description chapters.
RO
WO
R/W
R/WC
R/WO
R/WLO
Default
Bold
Read Only. In some cases, If a register is read only, writes to this register location
have no effect. However, in other cases, two separate registers are located at the
same location where a read accesses one of the registers and a write accesses the
other register. See the I/O and memory map tables for details.
Write Only. In some cases, If a register is write only, reads to this register location
have no effect. However, in other cases, two separate registers are located at the
same location where a read accesses one of the registers and a write accesses the
other register. See the I/O and memory map tables for details.
Read/Write. A register with this attribute can be read and written.
Read/Write Clear. A register bit with this attribute can be read and written.
However, a write of 1 clears (sets to 0) the corresponding bit and a write of 0 has
no effect.
Read/Write-Once. A register bit with this attribute can be written only once after
power up. After the first write, the bit becomes read only.
Read/Write, Lock-Once. A register bit with this attribute can be written to the non-
locked value multiple times, but to the locked value only once. After the locked
value has been written, the bit becomes read only.
When Chipset is reset, it sets its registers to predetermined default states. The
default state represents the minimum functionality feature set required to
successfully bring up the system. Hence, it does not represent the optimal system
configuration. It is the responsibility of the system initialization software to
determine configuration, operating parameters, and optional system features that
are applicable, and to program the Chipset registers accordingly.
Register bits that are highlighted in bold text indicate that the bit is implemented
in the Chipset. Register bits that are not implemented or are hardwired will remain
in plain text.
All bit(s) or bit-fields must be correctly dealt with by software. On reads, software must
use appropriate masks to extract the defined bits and not rely on reserved bits being
any particular value. On writes, software must ensure that the values of reserved bit
locations are preserved. Any Chipset configuration register or I/O or memory mapped
location not explicitly indicated in this document must be considered reserved.
PCI Devices and Functions
The Chipset incorporates a variety of PCI functions as shown in Table 9-106. These
functions are divided into six logical devices (B0:D30, B0:D31, B0:D29, B0:D28,
B0:D27 and B1:D8). D30 contains the DMI interface-to-PCI bridge and the AC’97 Audio
and Modem controller. D31 contains the PCI-to-LPC bridge, SATA controller, and the
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