82NM10 Datasheet, PDF (603/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Intel HD Audio Controller Registers (D27:F0)
Bit
Description
7:0 Stream Interrupt Enable (SIE) — R/W.
0 = Disable.
1 = Enable. When set to 1, the individual streams are enabled to generate an interrupt
when the corresponding status bits get set.
A stream interrupt will be caused as a result of a buffer with IOC = 1in the BDL entry
being completed, or as a result of a FIFO error (underrun or overrun) occurring. Control
over the generation of each of these sources is in the associated Stream Descriptor.
The streams are numbered and the SIE bits assigned sequentially, based on their order
in the register set.
Bit 0 = input stream 1
Bit 1 = input stream 2
Bit 2 = input stream 3
Bit 3 = input stream 4
Bit 4 = output stream 1
Bit 5 = output stream 2
Bit 6 = output stream 3
Bit 7 = output stream 4
18.2.13 INTSTS—Interrupt Status Register
(Intel HD Audio Controller—D27:F0)
Memory Address:HDBAR + 24h
Attribute:
RO
Default Value:
00000000hSize:32 bits
Bit
Description
31 Global Interrupt Status (GIS) — RO. This bit is an OR of all the interrupt status bits
in this register.
NOTE: This bit is not affected by the D3_HOT to D0 transition.
30 Controller Interrupt Status (CIS) — RO. Status of general controller interrupt.
0 = An interrupt condition did Not occur as described below.
1 = An interrupt condition occurred due to a Response Interrupt, a Response Buffer
Overrun Interrupt, or a SDIN State Change event. The exact cause can be
determined by interrogating other registers. This bit is an OR of all of the stated
interrupt status bits for this register.
29:8
NOTES:
1.
This bit is set regardless of the state of the corresponding interrupt enable bit,
but a hardware interrupt will not be generated unless the corresponding enable
bit is set.
2.
This bit is not affected by the D3_HOT to D0 transition.
Reserved
Datasheet
603