82NM10 Datasheet, PDF (362/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.1.16 GC—GPIO Control Register (LPC I/F — D31:F0)
Offset Address: 4Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bit
Bit
Description
7:5 Reserved.
4 GPIO Enable (EN) — R/W. This bit enables/disables decode of the I/O range pointed
to by the GPIO Base Address register (D31:F0:48h) and enables the GPIO function.
0 = Disable.
1 = Enable.
3:0 Reserved.
13.1.17 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
PIRQA – 60h, PIRQB – 61h, Attribute:R/W
PIRQC – 62h, PIRQD – 63h
80h
Size:8 bit
No
Power Well:Core
Bit
Description
7
Interrupt Routing Enable (IRQEN) — R/W.
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts
specified in bits[3:0].
1 = The PIRQ is not routed to the 8259.
NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are
being used. The value of this bit may subsequently be changed by the OS
when setting up for I/O APIC interrupt delivery mode.
6:4 Reserved
3:0 IRQ Routing — R/W. (ISA compatible.)
Value
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
IRQ
Reserved
Reserved
Reserved
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Value
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
IRQ
Reserved
IRQ9
IRQ10
IRQ11
IRQ12
Reserved
IRQ14
IRQ15
362
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