82NM10 Datasheet, PDF (69/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Pin States
Table 3-26.Power Plane and States for Output and I/O Signals (Sheet 4 of 4)
Signal Name
Power
Plane
During
PLTRST#⁶ /
RSMRST#⁷
Immediately
after
PLTRST#⁶ /
RSMRST#⁷
C3/C4
S1
S3_COLD13
S4/
S5
GPIO[7:6]
GPIO[15:12,10:8]
GPIO24
Core
Suspend
Suspend
GPIO25
Suspend
GPIO[28:26]
Suspend
GPIO33
GPIO34
GPIO[39:38]
Suspend
Core
Core
SPI_CS#
SPI_MOSI
SPI_ARB
SPI_CLK
Suspend
Suspend
Suspend
Suspend
Un-multiplexed GPIO Signals
Input
Input
Driven
Input
No Change
Input
No Change
Driven
Defined
Driven
Driven
Defined
High
High⁷
Defined Defined
Low
Low
Defined Defined
High
Low
Input
High
Low¹¹
Input
SPI Interface
High
High
Low
Low
High
High
Low
Low
Defined
Defined
Driven
Defined
Defined
Driven
High
High
Low
Low
High
High
Low
Low
Off
Driven
Defined
Defined
Defined
Off
Off
Off
High
High
Low
Low
Off
Driven
Define
d
Define
d
Define
d
Off
Off
Off
High
High
Low
Low
NOTES:
1.
NM10 drives these signals High after the CPU Reset.
2.
GPIO[18] will toggle at a frequency of approximately 1 Hz when the NM10 comes out of reset
3.
CPUPWRGD is an output that represents a logical AND of the NM10’s VRMPWRGD and PWROK signals, and
thus will be driven low by NM10 when either VRMPWRGD or PWROK are inactive. During boot, or during a
hard reset with power cycling, CPUPWRGD will be expected to transition from low to High.
4.
LAN Connect and EEPROM signals will either be “Defined” or “Off” in S3-S5 states depending upon whether
or not the LAN power planes are active.
5.
The state of the DPRSLPVR and DPRSTP# signals in C4 are high if Deeper Sleep is enabled or low if it is
disabled.
6.
The states of Vcc3_3 signals are taken at the times during PLTRST# and Immediately after PLTRST#.
7.
The states of VccSus3_3 signals are taken at the times during RSMRST# and Immediately after RSMRST#.
8.
NM10 drives these signals Low before PWROK rising and Low after the CPU Reset.
9.
GPIO[25] transitions from pulled high internally to actively driven within 100 ms of the deassertion of the
RSMRST# pin.
10. 10.SLP_S5# signals will be high in the S4 state.
11. Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which
time ACZ_RST# will be High and ACZ_BIT_CLK will be Running.
12. PETp/n[6:1] high until port is enabled by software.
13. In S3hot, signal states are platform implementation specific, as some external components and interfaces
may be powered when the NM10 is in the S3hot state.
Datasheet
69