82NM10 Datasheet, PDF (261/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Register and Memory Mapping
Table 9-108.Variable I/O Decode Ranges
Range Name
Mappable
ACPI
IDE Bus Master
Native IDE Command
Native IDE Control
USB UHCI Controller #1
USB UHCI Controller #2
USB UHCI Controller #3
USB UHCI Controller #4
SMBus
TCO
GPIO
Parallel Port
Serial Port 1
Serial Port 2
Floppy Disk Controller
LAN
LPC Generic 1
LPC Generic 2¹
LPC Generic 3
LPC Generic 4
I/O Trapping Ranges
Anywhere in 64 KB I/O Space
Anywhere in 64 KB I/O Space
Anywhere in 64 KB I/O Space
Anywhere in 64 KB I/O Space
Anywhere in 64 KB I/O Space
Anywhere in 64 KB I/O Space
Anywhere in 64 KB I/O Space
Anywhere in 64 KB I/O Space
Anywhere in 64 KB I/O Space
96 Bytes above ACPI Base
Anywhere in 64 KB I/O Space
3 Ranges in 64 KB I/O Space
8 Ranges in 64 KB I/O Space
8 Ranges in 64 KB I/O Space
2 Ranges in 64 KB I/O Space
Anywhere in 64 KB I/O Space
Anywhere in 64 KB I/O Space
Anywhere in 64 KB I/O Space
Anywhere in 64 KB I/O Space
Anywhere in 64 KB I/O Space
Anywhere in 64 KB I/O Space
Size
(Bytes)
64
16
8
4
32
32
32
32
32
32
64
8
8
8
8
64
4 to 256
4 to 256
4 to 256
4 to 256
1 to 256
Target
Power Management
IDE Unit
IDE Unit
IDE Unit
USB Unit 1
USB Unit 2
USB Unit 3
USB Unit 4
SMB Unit
TCO Unit
GPIO Unit
LPC Peripheral
LPC Peripheral
LPC Peripheral
LPC Peripheral
LAN Unit
LPC Peripheral
LPC Peripheral
LPC Peripheral
LPC Peripheral
Trap on Backbone
NOTE:
1.
Decode range size determined by D31:F0:ADh:bits 5:4
9.4
Memory Map
Table 9-109 shows (from the processor perspective) the memory ranges that the
Chipset decodes. Cycles that arrive from DMI that are not directed to any of the
internal memory targets that decode directly from DMI will be driven out on PCI unless
the Subtractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0). The Chipset may
then claim the cycle for the internal LAN controller.
PCI cycles generated by external PCI masters will be positively decoded unless they fall
in the PCI-to-PCI bridge memory forwarding ranges (those addresses are reserved for
PCI peer-to-peer traffic). If the cycle is not in the internal LAN controller’s range, it will
be forwarded up to DMI. Software must not attempt locks to the Chipset's memory-
mapped I/O ranges for EHCI and HPET. If attempted, the lock is not honored which
means potential deadlock conditions may occur.
Datasheet
261