82NM10 Datasheet, PDF (311/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
Table 11-114.Chipset Integrated LAN Controller CSR Space Register Address Map
Offset
Mnemonic
Register Name
08h–0Bh
Port
PORT Interface
0Ch–
0Dh
0Eh
0Fh
—
Reserved
EEPROM_CNTL EEPROM Control
—
Reserved
10h–13h
14h–17h
MDI_CNTL
REC_DMA_BC
Management Data Interface
Control
Receive DMA Byte Count
18h
19–1Ah
EREC_INTR
FLOW_CNTL
Early Receive Interrupt
Flow Control
1Bh
1Ch
1Dh
1Eh
1Fh
20h–3Ch
PMDR
GENCNTL
GENSTA
—
SMB_PCI
—
Power Management Driver
General Control
General Status
Reserved
SMB via PCI
Reserved
Default
0000 0000h
—
Type
R/W (special)
—
00
—
0000 0000h
R/W, RO, WO
—
R/W (special)
0000 0000h
00h
0000h
00h
00h
00h
—
27h
—
RO
R/W
RO, R/W
(special)
R/WC
R/W
RO
—
R/W
—
11.2.1
SCB_STA—System Control Block Status Word Register
(LAN Controller—B1:D8:F0)
Offset Address: 00h–01h
Default Value: 0000h
Attribute:
Size:
R/WC, RO
16 bits
The chipset’s integrated LAN controller places the status of its Command Unit (CU) and
Receive Unit (RC) and interrupt indications in this register for the processor to read.
Bit
Description
15 Command Unit (CU) Executed (CX) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit
position.
1 = Interrupt signaled because the CU has completed executing a command with its
interrupt bit set.
14 Frame Received (FR) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit
position.
1 = Interrupt signaled because the Receive Unit (RU) has finished receiving a frame.
Datasheet
311