82NM10 Datasheet, PDF (466/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

UHCI Controllers Registers
14.2.7
Note:
PORTSC[0,1]—Port Status and Control Register
I/O Offset:
RO,
only)
Port 0/2/4/6: Base + (10h–11h)Attribute:R/WC,
Port 1/3/5/7: Base + (12h–13h)R/W (Word writes
Default Value:
0080hSize:16 bits
For Function 0, this applies to Chipset USB ports 0 and 1; for Function 1, this applies to
Chipset USB ports 2 and 3; for Function 2, this applies to Chipset USB ports 4 and 5;
and for Function 3, this applies to Chipset USB ports 6 and 7.
After a power-up reset, global reset, or host controller reset, the initial conditions of a
port are: no device connected, Port disabled, and the bus line status is 00 (single-
ended 0).
Port Reset and Enable Sequence
When software wishes to reset a USB device it will assert the Port Reset bit in the Port
Status and Control register. The minimum reset signaling time is 10 mS and is enforced
by software. To complete the reset sequence, software clears the port reset bit. The
Intel UHCI controller must re-detect the port connect after reset signaling is complete
before the controller will allow the port enable bit to de set by software. This time is
approximately 5.3 uS. Software has several possible options to meet the timing
requirement and a partial list is enumerated below:
• Iterate a short wait, setting the port enable bit and reading it back to see if the
enable bit is set.
• Poll the connect status bit and wait for the hardware to recognize the connect prior
to enabling the port.
• Wait longer than the hardware detect time after clearing the port reset and prior to
enabling the port.
466
Datasheet