82NM10 Datasheet, PDF (387/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
3 Edge/Level Bank Select (LTIM) — WO. Disabled. Replaced by the edge/level
triggered control registers (ELCR, D31:F0:4D0h, D31:F0:4D1h).
2 ADI — WO.
0 = Ignored for the Chipset. Should be programmed to 0.
1 Single or Cascade (SNGL) — WO.
0 = Must be programmed to a 0 to indicate two controllers operating in cascade mode.
0 ICW4 Write Required (IC4) — WO.
1 = This bit must be programmed to a 1 to indicate that ICW4 needs to be
programmed.
13.4.3
ICW2—Initialization Command Word 2 Register
(LPC I/F—D31:F0)
Offset Address: Master Controller – 21h
Slave Controller – A1h
Default Value: All bits undefined
Attribute:
Size:
WO
8 bit /controller
ICW2 is used to initialize the interrupt controller with the five most significant bits of
the interrupt vector address. The value programmed for bits[7:3] is used by the
processor to define the base address in the interrupt vector table for the interrupt
routines associated with each IRQ on the controller. Typical ISA ICW2 values are 08h
for the master controller and 70h for the slave controller.
Bit
Description
7:3 Interrupt Vector Base Address — WO. Bits [7:3] define the base address in the
interrupt vector table for the interrupt routines associated with each interrupt request
level input.
2:0 Interrupt Request Level — WO. When writing ICW2, these bits should all be 0.
During an interrupt acknowledge cycle, these bits are programmed by the interrupt
controller with the interrupt to be serviced. This is combined with bits [7:3] to form the
interrupt vector driven onto the data bus during the second INTA# cycle. The code is a
three bit binary code:
Code
000b
001b
010b
011b
100b
101b
110b
111b
Master Interrupt
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Slave Interrupt
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
Datasheet
387