82NM10 Datasheet, PDF (156/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
S3_COLD
The SLP_S3# output signal can be used to cut power to the system core supply, since it
only goes active for the STR state (typically mapped to ACPI S3). Power must be
maintained to Chipset resume well, and to any other circuits that need to generate
Wake signals from the STR state.
Cutting power to the core may be done via the power supply, or by external FETs to the
motherboard.
The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core
supply, as well as power to the system memory, since the context of the system is
saved on the disk. Cutting power to the memory may be done via the power supply, or
by external FETs to the motherboard.
The SLP_S4# output signal is used to remove power to additional subsystems that are
powered during SLP_S3#.
SLP_S5# output signal can be used to cut power to the system core supply, as well as
power to the system memory, since the context of the system is saved on the disk.
Cutting power to the memory may be done via the power supply, or by external FETs to
the motherboard.
5.14.11.2 SLP_S4# and Suspend-To-RAM Sequencing
The system memory suspend voltage regulator is controlled by the Glue logic. The
SLP_S4# signal should be used to remove power to system memory rather than the
SLP_S5# signal. The SLP_S4# logic in Chipset provides a mechanism to fully cycle the
power to the DRAM and/or detect if the power is not cycled for a minimum time.
Note:
To utilize the minimum DRAM power-down feature that is enabled by the SLP_S4#
Assertion Stretch Enable bit (D31:F0:A4h bit 3), the DRAM power must be controlled
by the SLP_S4# signal.
5.14.11.3 PWROK Signal
The PWROK input should go active based on the core supply voltages becoming valid.
PWROK should go active no sooner than 100 ms after Vcc3_3 and Vcc1_5 have reached
their nominal values.
Note:
1. SYS_RESET# is recommended for implementing the system reset button. This
saves external logic that is needed if the PWROK input is used. Additionally, it
allows for better handling of the SMBus and processor resets, and avoids
improperly reporting power failures.
2. If the PWROK input is used to implement the system reset button, Chipset does not
provide any mechanism to limit the amount of time that the processor is held in
reset. The platform must externally ensure that maximum reset assertion
specifications are met.
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Datasheet