82NM10 Datasheet, PDF (634/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
Bit
Description
2 Fatal Error Detected (FED) — R/WC. This bit indicates a fatal error was detected.
0 = Fatal has not occurred.
1 = A fatal error occurred from a data link protocol error, link training error, buffer
overflow, or malformed TLP.
1 Non-Fatal Error Detected (NFED) — R/WC. This bit indicates a non-fatal error was
detected.
0 = Non-fatal has not occurred.
1 = A non-fatal error occurred from a poisoned TLP, unexpected completions,
unsupported requests, completer abort, or completer timeout.
0 Correctable Error Detected (CED) — R/WC. This bit indicates a correctable error
was detected.
0 = Correctable has not occurred.
1 = The port received an internal correctable error from receiver errors / framing
errors, TLP CRC error, DLLP CRC error, replay num rollover, replay timeout.
19.1.27 LCAP—Link Capabilities Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 4Ch–4Fh
Default Value: See bit description
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31:24 Port Number (PN) — RO. This field indicates the port number for the root port. This
value is different for each implemented port:
Function
D28:F0
D28:F1
D28:F2
D28:F3
Port #
1
2
3
4
Value of PN
Field
01h
02h
03h
04h
23:21 Reserved
20 Link Active Reporting Capable (LARC) — RO. Hardwired to 1 to indicate that this
port supports the optional capability of reporting the DL_Active state of the Data Link
Control and Management State Machine.
19:18 Reserved
17:15 L1 Exit Latency (EL1) — RO. Set to 010b to indicate an exit latency of 2 µs to 4 µs.
14:12 L0s Exit Latency (EL0) — RO. This field indicates as exit latency based upon
common-clock configuration.
LCLT.CCC
0
1
Value of EL0 (these bits)
MPC.UCEL (D28:F0/F1/F2/F3:D8h:bits20:18)
MPC.CCEL (D28:F0/F1/F2/F3:D8h:bits17:15)
NOTE: LCLT.CCC is at D28:F0/F1/F2/F3:50h:bit 6
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Datasheet