82NM10 Datasheet, PDF (58/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Signal Description
Table 2-20.Intel HD Audio Link Signals (Sheet 2 of 2)
Name^1,2
Type
Description
HDA_SDOUT
HDA_SDIN[2:0]
Intel High Definition Audio Serial Data Out: This signal is the
serial TDM data output to the codec(s). This serial output is double-
O
pumped for a bit rate of 48 Mb/s for Intel High Definition Audio.
NOTE: HDA_SDOUT is sampled at the rising edge of PWROK as a
functional strap. See Section 2.22.1 for more details. There is
a weak integrated pull-down resistor on the HDA_SDOUT pin.
Intel High Definition Audio Serial Data In [2:0]: These signals
I
are serial TDM data inputs from the three codecs. The serial input is
single-pumped for a bit rate of 24 Mb/s for Intel HD Audio. These
signals have integrated pull-down resistors that are always enabled.
1. Some signals have integrated pull-ups or pull-downs. Consult table in Section 3.1 for details.
2. Intel High Definition Audio have to configure through D30:F1:40h, bit 0: AZ#. This bit configure
the Intel High Definition Audio signals and BIOS need to set it to 1.
2.19 Serial Peripheral Interface (SPI)
Table 2-21.Serial Peripheral Interface (SPI) Signals
Name
Type
Description
SPI_CS#
SPI_MISO
SPI_MOSI
SPI_ARB
SPI_CLK
I/O
SPI Chip Select: This chip select signal is also used as the SPI bus
request signal.
I
SPI Master IN Slave OUT: This signal is the data input pin for the
chipset.
O
SPI Master OUT Slave IN: This signal is the data output pin for
the chipset.
I
SPI Arbitration: SPI_ARB is the SPI arbitration signal used to
arbitrate the SPI bus when Shared Flash is implemented.
O
SPI Clock: This signal is the SPI clock signal. During idle, the bus
owner will drive the clock signal low. 17.86 MHz.
2.20 General Purpose I/O Signals
Table 2-22.General Purpose I/O Signals (Sheet 1 of 2)
Name^1,2
GPIO49
GPIO48
GPIO[47:40]
GPIO[39:38]
GPIO37
GPIO36
Type
I/O
I/O
N/A
I/O
N/A
I/O
Tolerance
V_CPU_IO
3.3 V
N/A
3.3 V
N/A
3.3 V
Power
Well
V_CPU_IO
Core
N/A
Core
N/A
Core
Default
Native
Native
N/A
GPI
N/A
GPI
Description
Multiplexed with CPUPWRGD
Multiplexed with STRAP1#
Not implemented.
Unmultiplexed.
Not Implemented.
Unmultiplexed.
58
Datasheet