82NM10 Datasheet, PDF (431/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Datasheet
Bit
26
25
24:22
21
20
20:19
19
18
17
16
15
14
13
Description
SPI_STS — RO. This bit will be set if the SPI logic is generating an SMI#. This bit
is read only because the sticky status and enable bits associated with this
function are located in the SPI registers.
Reserved
Reserved
MONITOR_STS — RO. This bit will be set if the Trap/SMI logic has caused the
SMI. This will occur when the processor or a bus master accesses an assigned
register (or a sequence of accesses). See Section 10.1.32 through
Section 10.1.35 for details on the specific cause of the SMI.
PCI_EXP_SMI_STS — RO. PCI Express* SMI event occurred. This could be due
to a PCI Express PME event or Hot-Plug event.
Reserved
Reserved
INTEL_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each of
the SMI status bits in the Intel-Specific USB2 SMI Status Register ANDed with
the corresponding enable bits. This bit will not be active if the enable bits are not
set. Writes to this bit will have no effect.
LEGACY_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each
of the SMI status bits in the USB2 Legacy Support Register ANDed with the
corresponding enable bits. This bit will not be active if the enable bits are not set.
Writes to this bit will have no effect.
SMBus SMI Status (SMBUS_SMI_STS) — R/WC. Software clears this bit by
writing a 1 to it.
0 = This bit is set from the 64 kHz clock domain used by the SMBus. Software
must wait at least 15.63 us after the initial assertion of this bit before
clearing it.
1 = Indicates that the SMI# was caused by:
1. The SMBus Slave receiving a message that an SMI# should be caused, or
2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and
the
SMBALERT_DIS bit is cleared, or
3. The SMBus Slave receiving a Host Notify message and the
HOST_NOTIFY_INTREN and the SMB_SMI_EN bits are set, or
4. The Chipset detecting the SMLINK_SLAVE_SMI command while in the S0
state.
SERIRQ_SMI_STS — RO.
0 = SMI# was not caused by the SERIRQ decoder.
1 = Indicates that the SMI# was caused by the SERIRQ decoder.
NOTE: This is not a sticky bit
PERIODIC_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set at the rate determined by the PER_SMI_SEL bits. If the
PERIODIC_EN bit (PMBASE + 30h, bit 14) is also set, the Chipset generates
an SMI#.
TCO_STS — R/WC. Software clears this bit by writing a 1 to it.
0 = SMI# not caused by TCO logic.
1 = Indicates the SMI# was caused by the TCO logic. Note that this is not a wake
event.
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