82NM10 Datasheet, PDF (525/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

EHCI Controller Registers (D29:F7)
Bit
Description
4 Reserved
3 PME Clock (PME_CLK) — R/W (special). The Chipset reports 0, indicating that no PCI
clock is required to generate PME#.
2:0 Version (VER) — R/W (special). The Chipset reports 010b, indicating that it complies
with Revision 1.1 of the PCI Power Management Specification.
NOTES:
1.
Normally, this register is read-only to report capabilities to the power management
software. To report different power management capabilities, depending on the system in
which the Chipset is used, bits 15:11 and 8:6 in this register are writable when the
WRT_RDONLY bit (D29:F7:80h, bit 0) is set. The value written to this register does not
affect the hardware other than changing the value returned during a read.
2.
Reset: core well, but not D3-to-D0 warm reset.
16.1.19 PWR_CNTL_STS—Power Management Control/
Status Register (USB EHCI—D29:F7)
Address Offset: 54h–55h
Default Value: 0000h
Attribute:
Size:
R/W, R/WC, RO
16 bits
Bit
Description
15 PME Status — R/WC.
0 = Writing a 1 to this bit will clear it and cause the internal PME to deassert (if
enabled).
1 = This bit is set when the Chipset EHC would normally assert the PME# signal
independent of the state of the PME_En bit.
NOTE: This bit must be explicitly cleared by the operating system each time the
operating system is loaded.
14:13 Data Scale — RO. Hardwired to 00b indicating it does not support the associated Data
register.
12:9 Data Select — RO. Hardwired to 0000b indicating it does not support the associated
Data register.
8 PME Enable — R/W.
0 = Disable.
1 = Enable. Enables Chipset EHC to generate an internal PME signal when PME_Status
is 1.
NOTE: This bit must be explicitly cleared by the operating system each time it is
initially loaded.
7:2 Reserved
Datasheet
525