82NM10 Datasheet, PDF (421/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Bit
17
16:9
8
7:5
Description
Throttle Status (THTL_STS) — RO.
0 = No clock throttling is occurring (maximum processor performance).
1 = Indicates that the clock state machine is throttling the processor performance. This
could be due to the THT_EN bit or the FORCE_THTL bit being set.
Reserved
Force Thermal Throttling (FORCE_THTL) — R/W. Software can set this bit to force
the thermal throttling function.
0 = No forced throttling.
1 = Throttling at the duty cycle specified in THRM_DTY starts immediately, and no
SMI# is generated.
THRM_DTY — WO. This write-once field determines the duty cycle of the throttling
when the FORCE_THTL bit is set. The duty cycle indicates the approximate percentage
of time the STPCLK# signal is asserted while in the throttle mode. The STPCLK#
throttle period is 1024 PCICLKs. Note that the throttling only occurs if the system is in
the C0 state. For Netbook only, If in the C2, C3, or C4 state, no throttling occurs.
Once the THRM_DTY field is written, any subsequent writes will have no effect until
PLTRST# goes active.
THRM_DTY
000b
001b
010b
011b
100b
101b
110b
111b
Throttle Mode
50% (Default)
87.5%
75.0%
62.5%
50%
37.5%
25%
12.5%
PCI Clocks
512
896
768
640
512
384
256
128
4 THTL_EN — R/W. When set and the system is in a C0 state, it enables a processor-
controlled STPCLK# throttling. The duty cycle is selected in the THTL_DTY field.
0 = Disable
1 = Enable
3:1 THTL_DTY — R/W. This field determines the duty cycle of the throttling when the
THTL_EN bit is set. The duty cycle indicates the approximate percentage of time the
STPCLK# signal is asserted (low) while in the throttle mode. The STPCLK# throttle
period is 1024 PCICLKs.
THTL_DTY
000b
001b
010b
011b
100b
101b
110b
111b
Throttle Mode
50% (Default)
87.5%
75.0%
62.5%
50%
37.5%
25%
12.5%
PCI Clocks
512
896
768
640
512
384
256
128
0 Reserved
Datasheet
421