82NM10 Datasheet, PDF (474/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
Bit
Description
0 Primary Mode Native Enable (PNE) — R/W / RO.
Determines the mode that the primary channel is operating in.
0 = Primary controller operating in legacy (compatibility) mode.
1 = Primary controller operating in native PCI mode.
When MAP.MV (D31:F2:Offset 90:bits 1:0) is any value other than 00b, this bit is read-only (RO).
Software is responsible for clearing this bit before entering combined mode. The MAP.MV must be
program as 00b, and this bit is read/write (R/W).
If this bit is set by software, then the SNE bit (bit 2 of this register) must also be set by software. While
in theory these bits can be programmed separately, such a configuration is not supported by hardware.
15.1.6.2
When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h
Address Offset: 09h
Default Value: 01h
Attribute:
Size:
Bit
Description
7:0 Interface (IF) — RO.
Indicates the SATA Controller supports AHCI, rev 1.0.
RO
8 bits
15.1.7
SCC—Sub Class Code Register (SATA–D31:F2)
Address Offset: 0Ah
Default Value: See bit description
Attribute:
Size:
RO
8 bits
Bit
Description
7:0 Sub Class Code (SCC)
This field specifies the sub-class code of the controller, per the table below:
MAP.SMS
(D31:F2:Offset 90h:bit 7:6)
00b
01b
SCC Register Value
01h (IDE Controller)
06h (AHCI Controller)
15.1.8
BCC—Base Class Code Register
(SATA–D31:F2SATA–D31:F2)
Address Offset: 0Bh
Default Value: 01h
Bit
7:0 Base Class Code (BCC) — RO.
01h = Mass storage device
Attribute:
Size:
Description
RO
8 bits
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