82NM10 Datasheet, PDF (328/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LAN Controller Registers (B1:D8:F0)
11.3.4
ASF_CNTL_EN—ASF Control Enable Register
(ASF Controller—B1:D8:F0)
Offset Address: E3h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register is used to enable global processing as well as polling. GLOBAL ENABLE
controls all of the SMBus processing and packet creation.
Bit
Description
7 Global Enable (CENA_ALL) — R/W.
0 = Disable
1 = All control and polling enabled
6 Receive Enable (CENA_RX) — R/W.
0 = Disable
1 = TCO Receives enabled.
5 Transmit Enable (CENA_TX) — R/W.
0 = Disable
1 = SOS and RMCP Transmits enabled
4 ASF Polling Enable (CENA_APOL) — R/W.
0 = Disable
1 = Enable ASF Sensor Polling.
3 Legacy Polling Enable (CENA_LPOL) — R/W.
0 = Disable
1 = Enable Legacy Sensor Polling.
2:0 Number of Legacy Poll Devices (CENA_NLPOL) — R/W. This 3-bit value indicates how
many of the eight possible polling descriptors are active.
000 = First polling descriptor is active.
001 = First two polling descriptors are active.
...
111 = Enables all eight descriptors.
11.3.5
ENABLE—Enable Register
(ASF Controller—B1:D8:F0)
Offset Address: E4h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register provides the mechanism to enable internal SOS operations and to enable
the remote control functions.
Bit
Description
7 Enable OSHung ARPs (ENA_OSHARP) — R/W.
0 = Disable
1 = ASF will request all packets when in a OSHung state. This allows ASF to receive
ARP frames and respond as appropriate.
6 State-based Security Destination Port Select (ENA_SB0298) — R/W.
0 = State-based security will be honored on packets received on port 026Fh.
1 = Packets received on port 0298h will be honored.
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Datasheet