82NM10 Datasheet, PDF (666/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Serial Peripheral Interface (SPI)
Bit
Description
1 SPI Access Grant — RO. This bit is used by the software to know when the other SPI
master will not be initiating any long transactions on the SPI bus.
0 = Default
1 = It is set by hardware in response to software setting the SPI Access Request bit and
completing the Future Pending handshake with the LAN component.
NOTE: This bit is cleared in response to software clearing the SPI Access Request bit.
0 SPI Cycle In Progress (SCIP) — RO.
0 = Cycle Not in Progress (Default)
1 = Hardware sets this bit when software sets the SPI Cycle Go bit in the Command
register. This bit remains set until the cycle completes on the SPI interface.
Hardware automatically sets and clears this bit so that software can determine
when read data is valid and/or when it is safe to begin programming the next
command.
This bit reports 1b during the Status Register Polling sequence after reset deasserts; it
is cleared when that sequence completes.
NOTE: Software must only program the next command when this bit is 0.
21.1.2
SPIC—SPI Control Register
(SPI Memory Mapped Configuration Registers)
Memory Address:SPIBAR + 02h
Attribute:
R/W
Default Value:
4005hSize:16 bits
Bit
Description
15
14
13:8
7
6:4
3
SPI SMI# Enable — R/W.
0 = Disable.
1 = Enable. The SPI asserts an SMI# request when the Cycle Done Status bit is 1.
DATA Cycle— R/W.
0 = No data is delivered for this cycle, and the DBC and data fields themselves are
don't cares.
1 = There is data that corresponds to this transaction.
Data Byte Count (DBC) — R/W. This field specifies the number of bytes to shift in or
out during the data portion of the SPI cycle. The valid settings (in decimal) are any
value from 0 to 63. The number of bytes transferred is the value of this field plus 1.
For example, when this field is 000000b, then there is 1 byte to transfer and that
111111b means there are 64 bytes to transfer.
Reserved
Cycle Opcode Pointer — R/W. This field selects one of the programmed opcodes in
the Opcode Menu to be used as the SPI Command/Opcode. In the case of an Atomic
Cycle Sequence, this determines the second command.
Sequence Prefix Opcode Pointer — R/W. This field selects one of the two
programmed prefix opcodes for use when performing an Atomic Cycle Sequence. By
making this programmable, the Chipset supports flash devices that have different
opcodes for enabling writes to the data space vs. status register
0 = A value of 0 points to the opcode in the least significant byte of the Prefix Opcodes
register.
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Datasheet