82NM10 Datasheet, PDF (272/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Chipset Configuration Registers
10.1.14 ULD—Upstream Link Descriptor Register
Offset Address: 0110–0113h
Default Value: 00000001h
Attribute:
Size:
R/WO, RO
32-bit
Bit
Description
31:24
23:16
15:2
1
0
Target Port Number (PN) — R/WO. This field is programmed by platform BIOS to
match the port number of the (G)MCH/CPU RCRB that is attached to this RCRB.
Target Component ID (TCID) — R/WO. This field is programmed by platform BIOS
to match the component ID of the (G)MCH/CPU RCRB that is attached to this RCRB.
Reserved
Link Type (LT) — RO. This bit indicates that the link points to the (G)MCH/CPU
RCRB.
Link Valid (LV) — RO. This bit indicates that the link entry is valid.
10.1.15 ULBA—Upstream Link Base Address Register
Offset Address: 0118–011Fh
Default Value: 0000000000000000h
Attribute:
Size:
R/WO
64-bit
Bit
Description
63:32
31:0
Base Address Upper (BAU) — R/WO. This field is programmed by platform BIOS to
match the upper 32-bits of base address of the (G)MCH/CPU RCRB that is attached to
this RCRB.
Base Address Lower (BAL) — R/WO. This field is programmed by platform BIOS to
match the lower 32-bits of base address of the (G)MCH/CPU RCRB that is attached to
this RCRB.
10.1.16 RP1D—Root Port 1 Descriptor Register
Offset Address: 0120–0123h
Default Value: 01xx0002h
Attribute:
Size:
R/WO, RO
32-bit
Bit
Description
31:24
23:16
15:2
1
0
Target Port Number (PN) — RO. This field indicates that the target port number is
1h (root port #1).
Target Component ID (TCID) — R/WO. This field returns the value of the ESD.CID
(offset 0104h, bits 23:16) field programmed by platform BIOS, since the root port is
in the same component as the RCRB.
Reserved
Link Type (LT) — RO. This bit indicates that the link points to a root port.
Link Valid (LV) — RO. When FD.PE1D (offset 3418h, bit 16) is set, this link is not
valid (returns 0). When FD.PE1D is cleared, this link is valid (returns 1).
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Datasheet