82NM10 Datasheet, PDF (501/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15.3.1.2
Bit
24
23:20
19
18
17
16
15
14
13
12:8
7:5
4:0
Description
Supports Command List Override (SCLO) — R/WO. When set to 1, indicates that
the HBA supports the PxCMD.CLO bit and it's associated function. When cleared
to '0', The HBA is not capable of clearing the BSY and DRQ bits in the Status
register in order to issue a software reset if these bits are still set from a previous
operation.
Interface Speed Support (ISS) — R/WO. Indicates the maximum speed the SATA
controller can support on its ports.
2h =3.0 Gb/s.
Supports Non-Zero DMA Offsets (SNZO) — RO. Reserved, as per the AHCI
Revision 1.0 specification
Supports Port Selector Acceleration — RO. Port Selectors not supported.
Supports Port Multiplier (PMS) — R/WO. Chipset does not support port
multiplier. BIOS/SW shall write this bit to ‘0’ during AHCI initialization.
Supports Port Multiplier FIS Based Switching (PMFS) — RO. Reserved, as per the
AHCI Revision 1.0 specification.
NOTE: Port Multiplier not supported by Chipset.
PIO Multiple DRQ Block (PMD) — R/WO. The SATA controller supports PIO Multiple
DRQ Command Block
Slumber State Capable (SSC) — RO. The SATA controller supports the slumber
state.
Partial State Capable (PSC) — RO. The SATA controller supports the partial state.
Number of Command Slots (NCS) — RO. Hardwired to 1Fh to indicate support for
32 slots.
Reserved. Returns 0.
Number of Ports (NPS) — RO. Hardwired to 3h to indicate support for 4 ports.
Note that the number of ports indicated in this field may be more than the
number of ports indicated in the PI (ABAR + 0Ch) register.
GHC—Global Chipset Control Register (D31:F2)
Address Offset: ABAR + 04h–07h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
31 AHCI Enable (AE) — R/W. When set, indicates that an AHCI driver is loaded and the
controller will be talked to via AHCI mechanisms. This can be used by an Chipset that
supports both legacy mechanisms (such as SFF-8038i) and AHCI to know when the
controller will not be talked to as legacy.
When set, software will only talk to the Chipset using AHCI. The Chipset will not have to
allow command processing via both AHCI and legacy mechanisms. When cleared,
software will only talk to the Chipset using legacy mechanisms.
Software shall set this bit to 1 before accessing other AHCI registers.
Datasheet
501