82NM10 Datasheet, PDF (598/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Intel HD Audio Controller Registers (D27:F0)
18.2.5
18.2.6
INPAY—Input Payload Capability Register
(Intel HD Audio Controller—D27:F0)
Memory Address:HDBAR + 06h
Attribute:
RO
Default Value:
001DhSize:16 bits
Bit
Description
15:7
6:0
Reserved.
Input Payload Capability — RO. Hardwired to 1Dh indicating 29 word payload.
This field indicates the total output payload available on the link. This does not include
bandwidth used for response. This measurement is in 16-bit word quantities per 48
MHz frame. The default link clock of 24.000 MHz provides 500 bits per frame, or 31.25
words in total. 36 bits are used for response, leaving 29 words available for data
payload.
00h = 0 word
01h = 1 word payload.
.....
FFh = 256 word payload.
GCTL—Global Control Register
(Intel HD Audio Controller—D27:F0)
Memory Address:HDBAR + 08h
Attribute:
R/W
Default Value:
00000000hSize:32 bits
Bit
Description
31:9
8
7:2
1
Reserved.
Accept Unsolicited Response Enable — R/W.
0 = Unsolicited responses from the codecs are not accepted.
1 = Unsolicited response from the codecs are accepted by the controller and placed
into the Response Input Ring Buffer.
Reserved.
Flush Control — R/W.
0 = Flush Not in progress.
1 = Writing a 1 to this bit initiates a flush. When the flush completion is received by
the controller, hardware sets the Flush Status bit and clears this Flush Control bit.
Before a flush cycle is initiated, the DMA Position Buffer must be programmed
with a valid memory address by software, but the DMA Position Buffer bit 0 needs
not be set to enable the position reporting mechanism. Also, all streams must be
stopped (the associated RUN bit must be 0).
When the flush is initiated, the controller will flush the pipelines to memory to ensure
that the hardware is ready to transition to a D3 state. Setting this bit is not a critical
step in the power state transition if the content of the FIFIOs is not critical.
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