82NM10 Datasheet, PDF (616/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Intel HD Audio Controller Registers (D27:F0)
Bit
Description
31:0
Cyclic Buffer Length — R/W. Indicates the number of bytes in the complete cyclic
buffer. This register represents an integer number of samples. Link Position in Buffer
will be reset when it reaches this value.
Software may only write to this register after Global Reset, Controller Reset, or Stream
Reset has occurred. This value should be only modified when the RUN bit is 0. Once the
RUN bit has been set to enable the engine, software must not write to this register until
after the next reset is asserted, or transfer may be corrupted.
18.2.39 SDLVI—Stream Descriptor Last Valid Index Register
(Intel HD Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HDBAR + 8Ch
Input Stream[1]: HDBAR + ACh
Input Stream[2]: HDBAR + CCh
Input Stream[3]: HDBAR + ECh
Output Stream[0]: HDBAR + 10Ch
Output Stream[1]: HDBAR + 12Ch
Output Stream[2]: HDBAR + 14Ch
Output Stream[3]: HDBAR + 16Ch
Attribute: R/W
Default Value:
0000hSize:16 bits
Bit
Description
15:8
7:0
Reserved.
Last Valid Index — R/W. The value written to this register indicates the index for the
last valid Buffer Descriptor in BDL. After the controller has processed this descriptor, it
will wrap back to the first descriptor in the list and continue processing.
This field must be at least 1 (i.e., there must be at least 2 valid entries in the buffer
descriptor list before DMA operations can begin).
This value should only be modified when the RUN bit is 0.
18.2.40 SDFIFOW—Stream Descriptor FIFO Watermark Register
(Intel HD Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HDBAR + 8Eh
Input Stream[1]: HDBAR + AEh
Input Stream[2]: HDBAR + CEh
Input Stream[3]: HDBAR + EEh
Output Stream[0]: HDBAR + 10Eh
Output Stream[1]: HDBAR + 12Eh
Output Stream[2]: HDBAR + 14Eh
Output Stream[3]: HDBAR + 16Eh
Attribute: R/W
Default Value:
0004hSize:16 bits
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