82NM10 Datasheet, PDF (657/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
19.1.65 ULBA — Upstream Link Base Address Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 198h–19Fh
Default Value: See Description
Attribute:
Size:
RO
64 bits
Bit
Description
63:32 Base Address Upper (BAU) — RO. The RCRB of the Chipset is in 32-bit space.
31:0 Base Address Lower (BAL) — RO. This field matches the RCBA register
(D31:F0:Offset F0h) value in the LPC bridge.
19.1.66 PEETM — PCI Express Extended Test Mode Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 318h
Default Value: See Description
Attribute:
Size:
RO
8 bits
Bit
Description
7:3 Reserved
2 Scrambler Bypass Mode (BAU) — R/W.
0 = Normal operation. Scrambler and descrambler are used.
1 = Bypasses the data scrambler in the transmit direction and the data de-scrambler in
the receive direction.
NOTE: This functionality intended for debug/testing only.
NOTE: If bypassing scrambler with Chipset root port 1 in x4 configuration, each Chipset
root port must have this bit set.
1:0 Reserved
§
Datasheet
657