82NM10 Datasheet, PDF (504/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
Table 15-139.Port [1:0] DMA Register Address Map (Sheet 2 of 2)
ABAR +
Offset
Mnemonic
Register
180h–183h
184h–187h
188h–18Bh
18Ch–18Fh
190h–193h
194h–197h
198h–19Ch
19Ch–19Fh
1A0h–1A3h
1A4h–1A7h
1A8h–1ABh
1ACh–1AFh
1B0h–1B3h
1B4h–1B7h
1B8h–1BBh
1BCh–1FFh
200h–2FFh
P1CLB
P1CLBU
P1FB
P1FBU
P1IS
P1IE
P1CMD
—
P1TFD
P1SIG
P1SSTS
P1SCTL
P1SERR
P1SACT
P1CI
—
—
Port 1 Command List Base Address
Port 1 Command List Base Address Upper 32-Bits
Port 1 FIS Base Address
Port 1 FIS Base Address Upper 32-Bits
Port 1 Interrupt Status
Port 1 Interrupt Enable
Port 1 Command
Reserved
Port 1 Task File Data
Port 1 Signature
Port 1 Serial ATA Status
Port 1 Serial ATA Control
Port 1 Serial ATA Error
Port 1 Serial ATA Active
Port 1 Command Issue
Reserved
Reserved
15.3.2.1
PxCLB—Port [1:0] Command List Base Address Register
(D31:F2)
Address Offset: Port 0: ABAR + 100h
Port 1: ABAR + 180h
Attribute:
R/W, RO
Default Value: Undefined
Size:
32 bits
Bit
Description
31:10
Command List Base Address (CLB) — R/W. Indicates the 32-bit base for the
command list for this port. This base is used when fetching commands to execute. The
structure pointed to by this address range is 1 KB in length. This address must be 1-KB
aligned as indicated by bits 31:10 being read/write.
Note that these bits are not reset on a HBA reset.
9:0 Reserved — RO
504
Datasheet