82NM10 Datasheet, PDF (118/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
5.9.4.6
5.9.4.7
5.9.4.8
5.9.4.9
expand the number of interrupts. The polling interrupt service routine can call the
appropriate service routine, instead of providing the interrupt vectors in the vector
table. In this mode, the INTR output is not used and the microprocessor internal
Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is
achieved by software using a Poll command.
The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as
an interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads
the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte
returned during the I/O read contains a 1 in bit 7 if there is an interrupt, and the binary
code of the highest priority level in bits 2:0.
Cascade Mode
The PIC in Chipset has one master 8259 and one slave 8259 cascaded onto the master
through IRQ2. This configuration can handle up to 15 separate priority levels. The
master controls the slaves through a three bit internal bus. In Chipset, when the
master drives 010b on this bus, the slave controller takes responsibility for returning
the interrupt vector. An EOI command must be issued twice: once for the master and
once for the slave.
Edge and Level Triggered Mode
In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge
for the entire controller. In Chipset, this bit is disabled and a new register for edge and
level triggered mode selection, per interrupt input, is included. This is the Edge/Level
control Registers ELCR1 and ELCR2.
If an ELCR bit is 0, an interrupt request will be recognized by a low-to-high transition
on the corresponding IRQ input. The IRQ input can remain high without generating
another interrupt. If an ELCR bit is 1, an interrupt request will be recognized by a high
level on the corresponding IRQ input and there is no need for an edge detection. The
interrupt request must be removed before the EOI command is issued to prevent a
second interrupt from occurring.
In both the edge and level triggered modes, the IRQ inputs must remain active until
after the falling edge of the first internal INTA#. If the IRQ input goes inactive before
this time, a default IRQ7 vector is returned.
End of Interrupt (EOI) Operations
An EOI can occur in one of two fashions: by a command word write issued to the PIC
before returning from a service routine, the EOI command; or automatically when AEOI
bit in ICW4 is set to 1.
Normal End of Interrupt
In normal EOI, software writes an EOI command before leaving the interrupt service
routine to mark the interrupt as completed. There are two forms of EOI commands:
Specific and
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Datasheet