82NM10 Datasheet, PDF (154/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Functional Description
Table 5-64.Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of 2)
Restore Data
Restore Data
I/O
Addr
07h
08h
# of
Rds
2
6
Access
Data
1
DMA Chan 3 base count low
byte
2
DMA Chan 3 base count high
byte
1
DMA Chan 0–3 Command²
2
DMA Chan 0–3 Request
20h
12
3
DMA Chan 0 Mode:
Bits(1:0) = 00
4
DMA Chan 1 Mode:
Bits(1:0) = 01
5
DMA Chan 2 Mode:
Bits(1:0) = 10
6
DMA Chan 3 Mode: Bits(1:0)
= 11.
1
PIC ICW2 of Master
controller
2
PIC ICW3 of Master
controller
3
PIC ICW4 of Master
controller
4
PIC OCW1 of Master
controller²
5
PIC OCW2 of Master
controller
6
PIC OCW3 of Master
controller
7
PIC ICW2 of Slave controller
8
PIC ICW3 of Slave controller
9
PIC ICW4 of Slave controller
10
PIC OCW1 of Slave
controller¹
11
PIC OCW2 of Slave controller
12
PIC OCW3 of Slave controller
I/O
Addr
# of
Rds
Access
Data
C8h 2
CAh 2
CCh 2
CEh 2
D0h 6
1
DMA Chan 6 base address
low byte
2
DMA Chan 6 base address
high byte
1
DMA Chan 6 base count
low byte
2
DMA Chan 6 base count
high byte
1
DMA Chan 7 base address
low byte
2
DMA Chan 7 base address
high byte
1
DMA Chan 7 base count
low byte
2
DMA Chan 7 base count
high byte
1
DMA Chan 4–7
Command¹
2
DMA Chan 4–7 Request
3
DMA Chan 4 Mode:
Bits(1:0) = 00
4
DMA Chan 5 Mode:
Bits(1:0) = 01
5
DMA Chan 6 Mode:
Bits(1:0) = 10
6
DMA Chan 7 Mode:
Bits(1:0) = 11.
NOTES:
1.
Bits 5, 3, 1, and 0 return 0.
2.
The OCW1 register must be read before entering ALT access mode.
154
Datasheet