82NM10 Datasheet, PDF (47/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Signal Description
2.6
PCI Interface
Table 2-8. PCI Interface Signals (Sheet 1 of 3)
Name
AD[31:0]
C/BE[3:0]#
DEVSEL#
FRAME#
IRDY#
Type
Description
PCI Address/Data: AD[31:0] is a multiplexed address and data bus.
During the first clock of a transaction, AD[31:0] contain a physical
I/O address (32 bits). During subsequent clocks, AD[31:0] contain data.
chipset will drive all 0s on AD[31:0] during the address phase of all PCI
Special Cycles.
Bus Command and Byte Enables: The command and byte enable
signals are multiplexed on the same PCI pins. During the address phase
of a transaction, C/BE[3:0]B define the bus command. During the data
phase, C/BE[3:0]B define the Byte Enables.
C/BE[3:0]# Command Type
0000b
Interrupt Acknowledge
0001b
Special Cycle
0010b
I/O Read
0011b
I/O Write
I/O
0110b
Memory Read
0111b
Memory Write
1010b
Configuration Read
1011b
Configuration Write
1100b
Memory Read Multiple
1110b
Memory Read Line
1111b
Memory Write and Invalidate
All command encodings not shown are reserved. chipset does not
decode reserved values, and therefore will not respond if a PCI master
generates a cycle using one of the reserved values.
Device Select: chipset asserts DEVSELB to claim a PCI transaction. As
an output, chipset asserts DEVSEL# when a PCI master peripheral
attempts an access to an internal chipset address or an address
I/O destined DMI (main memory or graphics). As an input, DEVSEL#
indicates the response to an chipset-initiated transaction on the PCI
bus. DEVSEL# is tri-stated from the leading edge of PLTRST#.
DEVSEL# remains tri-stated by chipset until driven by a target device.
Cycle Frame: The current initiator drives FRAME# to indicate the
beginning and duration of a PCI transaction. While the initiator asserts
FRAME#, data transfers continue. When the initiator negates FRAME#,
I/O the transaction is in the final data phase. FRAME# is an input to chipset
when chipset is the target, and FRAME# is an output from chipset when
chipset is the initiator. FRAME# remains tri-stated by chipset until
driven by an initiator.
Initiator Ready: IRDY# indicates chipset's ability, as an initiator, to
complete the current data phase of the transaction. It is used in
conjunction with TRDY#. A data phase is completed on any clock both
IRDY# and TRDY# are sampled asserted. During a write, IRDY#
I/O indicates chipset has valid data present on AD[31:0]. During a read, it
indicates chipset is prepared to latch data. IRDY# is an input to chipset
when chipset is the target and an output from chipset when chipset is
an initiator. IRDY# remains tri-stated by chipset until driven by an
initiator.
Datasheet
47