82NM10 Datasheet, PDF (371/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
Note:
Bit
Description
8 FWH_C0_EN — R/W. This bit enables decoding two 512-KB Firmware Hub memory
ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FFC00000h – FFC7FFFFh
FF800000h – FF87FFFFh
7 FWH_Legacy_F_EN — R/W. This enables the decoding of the legacy 128-K range at
F0000h – FFFFFh.
0 = Disable.
1 = Enable the following legacy ranges for the Firmware Hub
F0000h – FFFFFh
6 FWH_Legacy_E_EN — R/W. This enables the decoding of the legacy 128-K range at
E0000h – EFFFFh.
0 = Disable.
1 = Enable the following legacy ranges for the Firmware Hub
E0000h – EFFFFh
5:4 Reserved
3 FWH_70_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FF70 0000h – FF7F FFFFh
FF30 0000h – FF3F FFFFh
2 FWH_60_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FF60 0000h – FF6F FFFFh
FF20 0000h – FF2F FFFFh
1 FWH_50_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FF50 0000h – FF5F FFFFh
FF10 0000h – FF1F FFFFh
0 FWH_40_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FF40 0000h – FF4F FFFFh
FF00 0000h – FF0F FFFFh
This register effects the BIOS decode regardless of whether the BIOS is resident on LPC
or SPI. The concept of Feature Space does not apply to SPI-based flash. The chipset
simply decodes these ranges as memory accesses when enabled for the SPI flash
interface.
Datasheet
371