82NM10 Datasheet, PDF (367/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.1.23 GEN2_DEC—LPC I/F Generic Decode Range 2Register
(LPC I/F—D31:F0)
Offset Address: 88h – 8Bh
Default Value: 00000000h
Attribute:
Size:
Power Well:
R/W
32 bit
Core
Bit
Description
31:24 Reserved
23:18
Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates
that any value in the corresponding address bit in a received cycle will be treated as a
match. The corresponding bit in the Address field, below, is ignored. The mask is only
provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
17:16 Reserved
15:2 Generic I/O Decode Range 2Base Address (GEN1_BASE) — R/W.
NOTE: The Chipset does not provide decode down to the word or byte level.
1 Reserved
0 Generic Decode Range 2Enable (GEN2_EN) — R/W.
0 = Disable.
1 = Enable the GEN2 I/O range to be forwarded to the LPC I/F
13.1.24 GEN3_DEC—LPC I/F Generic Decode Range 3Register
(LPC I/F—D31:F0)
Offset Address: 8Ch – 8Eh
Default Value: 00000000h
Attribute:
Size:
Power Well:
R/W
32 bit
Core
Bit
Description
31:24 Reserved
23:18
Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates
that any value in the corresponding address bit in a received cycle will be treated as a
match. The corresponding bit in the Address field, below, is ignored. The mask is only
provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
17:16 Reserved
15:2 Generic I/O Decode Range 3Base Address (GEN3_BASE) — R/W.
NOTE: The Chipset does not provide decode down to the word or byte level.
1 Reserved
0 Generic Decode Range 3Enable (GEN3_EN) — R/W.
0 = Disable.
1 = Enable the GEN3 I/O range to be forwarded to the LPC I/F
Datasheet
367