82NM10 Datasheet, PDF (496/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15.1.44 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2)
Address Offset: E4h–E7h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bits
Description
31:0
BIST FIS Transmit Data 1 — R/W. The data programmed into this register will form
the contents of the second DWord of any BIST FIS initiated by the Chipset. This register
is not port specific; its contents will be used for BIST FIS initiated on any port. Although
the 2nd and 3rd DWs of the BIST FIS are only meaningful when the “T” bit of the BIST
FIS is set to indicate “Far-End Transmit mode”, this register’s contents will be transmitted
as the BIST FIS 2nd DW regardless of whether or not the “T” bit is indicated in the BFCS
register (D31:F2:E0h).
15.1.45 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)
Address Offset: E8h–EBh
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bits
Description
31:0
BIST FIS Transmit Data 2 — R/W. The data programmed into this register will form
the contents of the third DWord of any BIST FIS initiated by the Chipset. This register is
not port specific; its contents will be used for BIST FIS initiated on any port. Although
the 2nd and 3rd DWs of the BIST FIS are only meaningful when the “T” bit of the BIST
FIS is set to indicate “Far-End Transmit mode”, this register’s contents will be transmitted
as the BIST FIS 3rd DW regardless of whether or not the “T” bit is indicated in the BFCS
register (D31:F2:E0h).
15.2
Bus Master IDE I/O Registers (D31:F2)
The bus master IDE function uses 16 bytes of I/O space, allocated via the BAR register,
located in Device 31:Function 2 Configuration space, offset 20h. All bus master IDE I/O
space registers can be accessed as byte, word, or DWord quantities. Reading reserved
bits returns an indeterminate, inconsistent value, and writes to reserved bits have no
effect (but should not be attempted). These registers are only used for legacy
operation. Software must not use these registers when running AHCI. The description
of the I/O registers is shown in Table 15-136.
Table 15-136.Bus Master IDE I/O Register Address Map
BAR+
Offset
Mnemonic
Register
00
BMICP Command Register Primary
01
—
Reserved
02
BMISP Bus Master IDE Status Register Primary
03
—
Reserved
Default
00h
—
00h
—
Type
R/W
RO
R/W, R/
WC, RO
RO
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