82NM10 Datasheet, PDF (626/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
19.1.7
SCC—Sub Class Code Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 0Ah
Default Value: 04h
Bit
7:0 Sub Class Code (SCC) — RO.
04h = PCI-to-PCI bridge.
Attribute:
Size:
Description
RO
8 bits
19.1.8
BCC—Base Class Code Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 0Bh
Default Value: 06h
Attribute:
Size:
Bit
Description
7:0 Base Class Code (BCC) — RO.
06h = Indicates the device is a bridge device.
RO
8 bits
19.1.9
CLS—Cache Line Size Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 0Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0 Base Class Code (BCC) — R/W. This is read/write but contains no functionality, per
the PCI Express* Base Specification.
19.1.10 PLT—Primary Latency Timer Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 0Dh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:3 Latency Count. Reserved per the PCI Express* Base Specification.
2:0 Reserved
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