82NM10 Datasheet, PDF (498/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15.2.2
BMIS[P,S]—Bus Master IDE Status Register (D31:F2)
Address Offset: Primary: BAR + 02h
Secondary: BAR + 0Ah
Default Value: 00h
Attribute:
Size:
R/W, R/WC, RO
8 bits
Bit
Description
7 PRD Interrupt Status (PRDIS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when the host controller execution of a PRD that has its PRD_INT bit
set.
6 Drive 1 DMA Capable — R/W.
0 = Not Capable.
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that
drive 1 for this channel is capable of DMA transfers, and that the controller has
been initialized for optimum performance. The Chipset does not use this bit. It is
intended for systems that do not attach BMIDE to the PCI bus.
5 Drive 0 DMA Capable — R/W.
0 = Not Capable
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that
drive 0 for this channel is capable of DMA transfers, and that the controller has
been initialized for optimum performance. The Chipset does not use this bit. It is
intended for systems that do not attach BMIDE to the PCI bus.
4:3 Reserved. Returns 0.
2 Interrupt — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set when a device FIS is received with the ‘I’ bit set, provided that software has not
disabled interrupts via the IEN bit of the Device Control Register (see chapter 5 of
the Serial ATA Specification, Revision 1.0a).
1 Error — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when the controller encounters a target abort or master abort when
transferring data on PCI.
0 Bus Master IDE Active (ACT) — RO.
0 = This bit is cleared by the Chipset when the last transfer for a region is performed,
where EOT for that region is set in the region descriptor. It is also cleared by the
Chipset when the Start Bus Master bit (D31:F2:BAR+ 00h, bit 0) is cleared in the
Command register. When this bit is read as a 0, all data transferred from the drive
during the previous bus master command is visible in system memory, unless the
bus master command was aborted.
1 = Set by the Chipset when the Start bit is written to the Command register.
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