82NM10 Datasheet, PDF (59/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Signal Description
Table 2-22.General Purpose I/O Signals (Sheet 2 of 2)
Name^1,2
GPIO35
GPIO34
GPIO33
GPIO32
GPIO31
GPIO30
GPIO29
GPIO28
GPIO27
GPIO26
GPIO25
GPIO24
Type Tolerance
N/A
N/A
I/O
3.3 V
I/O
3.3 V
N/A
N/A
I/O
3.3 V
I/O
3.3 V
I/O
3.3 V
I/O
3.3 V
I/O
3.3 V
I/O
3.3 V
I/O
3.3 V
I/O
3.3 V
Power
Well
N/A
Core
Core
N/A
Resume
Resume
Resume
Resume
Resume
Resume
Resume
Resume
GPIO23
GPIO22
GPIO[21:18]
GPIO17
GPIO16
GPIO[15:12]
GPIO11
GPIO[10:8]
GPIO[7:6]
GPIO[5:2]
GPIO1
GPIO0
I/O
I/O
N/A
I/O
N/A
I/O
I/O
I/O
I/O
I/OD
I/O
I/O
3.3 V
3.3 V
N/A
3.3 V
N/A
3.3 V
3.3 V
3.3 V
3.3 V
5V
5V
3.3 V
Core
Core
N/A
Core
N/A
Resume
Resume
Resume
Core
Core
Core
Core
Default
Description
N/A
GPO
GPO
N/A
Native
Native
Native
GPO
GPO
GPO
GPO
GPO
Native
GPI
N/A
GPO
N/A
GPI
Native
GPI
GPI
GPI
GPI
GPI
Not Implemented.
Unmultiplexed.
Unmultiplexed.
Not Implemented.
Multiplexed with OC7#
Multiplexed with OC6#
Multiplexed with OC5#
Unmultiplexed.
Unmultiplexed.
Unmultiplexed.
Unmultiplexed.
Unmultiplexed. Not cleared by
CF9h reset event.
Multiplexed with LDRQ1#
Unmultiplexed.
Not Implemented
Multiplexed with STRAP2#.
Not Implemented
Unmultiplexed.
Multiplexed with SMBALERT#
Unmultiplexed.
Unmultiplexed.
Multiplexed with PIRQ[H:E]#.
Unmultiplexed.
Multiplexed with BM_BUSY#.
1. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either an
SMI# or an SCI, but not both.
2. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO signals
are not driven high into powered-down planes. Some chipset GPIOs may be connected to pins on
devices that exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core
power (PWROK low) or a Power Button Override event will result in the Intel chipset driving a pin
to a logic 1 to another device that is powered down.
Datasheet
59