82NM10 Datasheet, PDF (556/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SMBus Controller Registers (D31:F3)
17.1.4
Note:
PCISTS—PCI Status Register (SMBUS—D31:F3)
Address:
06h–07h
Default Value: 0280h
Attributes:
Size:
RO, R/WC
16 bits
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
17.1.5
Bit
Description
15
14
13
12
11
10:9
8
7
6
5
4
3
2:0
Detected Parity Error (DPE) — R/WC.
0 = No parity error detected.
1 = Parity error detected.
Signaled System Error (SSE) — R/WC.
0 = No system error detected.
1 = System error detected.
Received Master Abort (RMA) — RO. Hardwired to 0.
Received Target Abort (RTA) — RO. Hardwired to 0.
Signaled Target Abort (STA) — R/WC.
0 = Chipset did Not terminate transaction for this function with a target abort.
1 = The function is targeted with a transaction that the Chipset terminates with a
target abort.
DEVSEL# Timing Status (DEVT) — RO. This 2-bit field defines the timing for
DEVSEL# assertion for positive decode.
01 = Medium timing.
Data Parity Error Detected (DPED) — RO. Hardwired to 0.
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
User Definable Features (UDF) — RO. Hardwired to 0.
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
Capabilities List (CAP_LIST) — RO. Hardwired to 0 because there are no capability
list structures in this function
Interrupt Status (INTS) — RO. This bit indicates that an interrupt is pending. It is
independent from the state of the Interrupt Enable bit in the PCI Command register.
Reserved
RID—Revision Identification Register (SMBUS—D31:F3)
Offset Address: 08h
Default Value: See bit description
Bit
7:0 Revision ID — RO.
Attribute:
Size:
Description
RO
8 bits
556
Datasheet