82NM10 Datasheet, PDF (494/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

SATA Controller Registers (D31:F2)
15.1.40 ATC—APM Trapping Control Register (SATA–D31:F2)
Address Offset: C0h
Default Value: 00h
.
Bit
Attribute:
Size:
Description
R/W
8 bits
7:4 Reserved
3 Secondary Slave Trap (SST) — R/W. Enables trapping and SMI# assertion on legacy
I/O accesses to 170h–177h and 376h. The active device on the secondary interface
must be device 1 for the trap and/or SMI# to occur.
2 Secondary Master Trap (SMT) — R/W. Enables trapping and SMI# assertion on
legacy I/O accesses to 170h–177h and 376h. The active device on the secondary
interface must be device 0 for the trap and/or SMI# to occur.
1 Primary Slave Trap (PST) — R/W. Enables trapping and SMI# assertion on legacy I/
O accesses to 1F0h–1F7h and 3F6h. The active device on the primary interface must be
device 1 for the trap and/or SMI# to occur.
0 Primary Master Trap (PMT) — R/W. Enables trapping and SMI# assertion on legacy
I/O accesses to 1F0h–1F7h and 3F6h. The active device on the primary interface must
be device 0 for the trap and/or SMI# to occur.
15.1.41 ATS—APM Trapping Status Register (SATA–D31:F2)
Address Offset: C4h
Default Value: 00h
.
Bit
Attribute:
Size:
Description
R/WC
8 bits
7:4 Reserved
3 Secondary Slave Trap (SST) — R/WC. Indicates that a trap occurred to the
secondary slave device.
2 Secondary Master Trap (SPT) — R/WC. Indicates that a trap occurred to the
secondary master device.
1 Primary Slave Trap (PST) — R/WC. Indicates that a trap occurred to the primary
slave device.
0 Primary Master Trap (PMT) — R/WC. Indicates that a trap occurred to the primary
master device.
15.1.42 SP — Scratch Pad Register (SATA–D31:F2)
Address Offset: D0h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
.
Bit
Description
31:0 Data (DT) — R/W. This is a read/write register that is available for software to use. No
hardware action is taken on this register.
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