82NM10 Datasheet, PDF (445/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

LPC Interface Bridge Registers (D31:F0)
13.10.1 GPIO_USE_SEL—GPIO Use Select Register
Offset Address: GPIOBASE + 00h
Default Value: 1F2AF7FFh
Attribute:
Size:
R/W
32-bit
Lockable:
No
Power Well:
Core for 0:7, 16:23,
Resume for 8:15, 24:31
Bit
Description
31:0
GPIO_USE_SEL[31:0] — R/W. Each bit in this register enables the corresponding
GPIO (if it exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
NOTES:
1.
The following bits are always 1 because they are unmuxed: 6:10,12:15, 24:25
2.
The following bits are not implemented because they are determined by the
configuration: 16, 18, 20, 32
3.
If GPIO[n] does not exist, then the bit in this register will always read as 0 and
writes will have no effect.
4.
After a full reset (RSMRST#) all multiplexed signals in the resume and core
wells are configured as their default function. After just a PLTRST#, the GPIO in
the core well are configured as their default function.
5.
When configured to GPIO mode, the multiplexing logic will present the inactive
state to native logic that uses the pin as an input.
6.
All GPIOs are reset to the default state by CF9h reset except GPIO24
13.10.2 GP_IO_SEL—GPIO Input/Output Select Register
Offset Address: GPIOBASE +04h
Default Value: E0E8FFFFh
Lockable:
No
Attribute:
Size:
Power Well:
R/W
32-bit
Core for 0:7, 16:23,
Resume for 8:15, 24:31
Bit
Description
31:0
GP_IO_SEL[31:0] — R/W. When configured in native mode (GPIO_USE_SEL[n] is
0), writes to these bits have no effect. The value reported in this register is undefined
when programmed as native mode.
0 = Output. The corresponding GPIO signal is an output.
1 = Input. The corresponding GPIO signal is an input.
Datasheet
445