82NM10 Datasheet, PDF (605/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

Intel HD Audio Controller Registers (D27:F0)
18.2.15 SSYNC—Stream Synchronization Register
(Intel HD Audio Controller—D27:F0)
Memory Address:HDBAR + 34h
Attribute:
R/W
Default Value:
00000000hSize:32 bits
Bit
Description
31:8
7:0
Reserved
Stream Synchronization (SSYNC) — R/W.
0 = Data is Not blocked from being sent on or received from the link
1 = The set bits block data from being sent on or received from the link. Each bit
controls the associated stream descriptor (i.e., bit 0 corresponds to the first stream
descriptor, etc.)
To synchronously start a set of DMA engines, these bits are first set to 1. The RUN bits
for the associated stream descriptors are then set to 1 to start the DMA engines. When
all streams are ready (FIFORDY =1), the associated SSYNC bits can all be set to 0 at
the same time, and transmission or reception of bits to or from the link will begin
together at the start of the next full link frame.
To synchronously stop the streams, first these bits are set, and then the individual RUN
bits in the stream descriptor are cleared by software.
If synchronization is not desired, these bits may be left as 0, and the stream will simply
begin running normally when the stream’s RUN bit is set.
The streams are numbered and the SIE bits assigned sequentially, based on their order
in the register set.
Bit 0 = input stream 1
Bit 1 = input stream 2
Bit 2 = input stream 3
Bit 3 = input stream 4
Bit 4 = output stream 1
Bit 5 = output stream 2
Bit 6 = output stream 3
Bit 7 = output stream 4
18.2.16 CORBLBASE—CORB Lower Base Address Register
(Intel HD Audio Controller—D27:F0)
Memory Address:HDBAR + 40h
Attribute:
R/W, RO
Default Value:
00000000hSize:32 bits
Bit
Description
31:7
6:0
CORB Lower Base Address — R/W. This field is the lower address of the Command
Output Ring Buffer, allowing the CORB base address to be assigned on any 128-B
boundary. This register field must not be written when the DMA engine is running or the
DMA transfer may be corrupted.
CORB Lower Base Unimplemented Bits — RO. Hardwired to 0. This requires the
CORB to be allocated with 128B granularity to allow for cache line fetch optimizations.
Datasheet
605