82NM10 Datasheet, PDF (656/671 Pages) Intel Corporation – Intel® NM10 Family Express Chipset

PCI Express* Configuration Registers
19.1.63 ESD — Element Self Description Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 184h–187h
Default Value: See Description
Attribute:
Size:
RO
32 bits
Bit
Description
31:24 Port Number (PN) — RO. This field indicates the ingress port number for the root
port. There is a different value per port:
Port #
1
2
3
4
Value
01h
02h
03h
04h
23:16
Component ID (CID) — RO. This field returns the value of the ESD.CID field (Chipset
Configuration Space: Offset 0104h:bits 23:16) of the chip configuration section, that is
programmed by platform BIOS, since the root port is in the same component as the
RCRB.
15:8 Number of Link Entries (NLE) — RO. (Default value is 01h). This field indicates one
link entry (corresponding to the RCRB).
7:4 Reserved.
3:0 Element Type (ET) — RO. (Default value is 0h). This field indicates that the element
type is a root port.
19.1.64 ULD — Upstream Link Description Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 190h–193h
Default Value: 00000001h
Attribute:
Size:
RO
32 bits
Bit
Description
31:24 Target Port Number (PN) — RO. This field indicates the port number of the RCRB.
23:16
Target Component ID (TCID) — RO. This field returns the value of the ESD.CID field
(Chipset Configuration Space: Offset 0104h:bits 23:16) of the chip configuration
section, that is programmed by platform BIOS, since the root port is in the same
component as the RCRB.
15:2 Reserved.
1 Link Type (LT) — RO. This bit indicates that the link points to the Chipset RCRB.
0 Link Valid (LV) — RO. This bit indicates that this link entry is valid.
656
Datasheet